Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby

ABSTRACT

Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, which can reproduce a profile of a gate electrode in a stable manner. The method includes forming an active pattern on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, forming a gate insulating layer on the channel regions, and forming a patterned gate electrode on the gate insulating layer while maintaining a shape conformal to the active pattern.

This application claims priority from Korean Patent Application No.10-2004-0049663 filed on Jun. 29, 2004 in the Korean IntellectualProperty Office, the contents of which are incorporated herein byreference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a multi-gate transistor having a gateelectrode with improved performance and a fabrication method thereof.

2. Description of the Related Art

Multi-gate transistors having a double-gate structure or a tri-gatestructure have been developed for next-generation devices. These devicesovercome degradation of performance due to a reduction of gate length(Lg) accompanied with scale down in devices (Kunihiro Suzuki et al.,IEEE 1993 “Scaling Theory for Double-Gate SOI MOSFETs”; Robert Chau,SSDM 2002, “Advanced Depleted-Substrate Transistors: Single-Gate,Double-Gate and Tri-Gate”; Z. Krivokapic, SSDM 2003, “High Performance45 nm CMOS Technology with 20 nm Multi-Gate Devices”; Jeong-Hwan Yang,IEDM 2003, “Fully Working 6T-SRAM Cell with 45 nm Gate Length TripleGate Transistors”).

A multi-gate transistor having a double-gate or tri-gate structure has ahigher tolerance on the thickness (Tsi) of a fully depleted regioncompared with a single-gate transistor.

Such a general multi-gate transistor structure includes an activepattern formed by patterning a single crystalline silicon body on aninsulating layer of a silicon-on-insulator (SOI) wafer and a gateelectrode formed on a side and/or an upper surface of the activepattern.

To fabricate a conventional multi-gate transistor, an active pattern isformed by patterning a silicon body formed on an insulating layer.Polysilicon for forming a gate electrode is deposited on a lateralsurface and/or an upper surface of the active pattern. Here, theunderlying active pattern makes the entire surface of polysilicondeposited uneven. Thus, it is quite difficult to perform aphotolithography process for forming the gate electrode. To solve thisproblem, a planarizing process using chemical mechanical polishing (CMP)is additionally performed after depositing a thick layer of polysilicon.

However, in the depositing the polysilicon, the thickness of polysilicondeposited is not uniform, resulting in a deviation in the thickness ofpolysilicon deposited throughout the surface. In the CMP process basedon time control, a deviation in the thickness of polysilicon polishedthroughout the surface may also be generated. The deviation in thethickness of polysilicon makes it difficult to control the thickness ofthe gate electrode. For example, when it is intended to depositpolysilicon to a thickness of several hundreds to several thousands ofAngstroms, use of conventional CMP may cause a thickness deviation ofseveral hundred angstroms across the surface of deposited polysilicon.Thus, it is difficult to control the thickness of a gate electrodestructure, ultimately resulting in a degradation of electricalcharacteristics of the transistor.

SUMMARY OF THE INVENTION

The present invention provides a method of fabricating a multi-gatetransistor having improved performance, in which a profile of a gateelectrode formed on a gate insulating layer of the multi-gate transistorcan be controlled in a stable manner.

The present invention also provides a multi-gate transistor fabricatedby the method.

According to an aspect of the present invention, there is provided amethod of fabricating a multi-gate transistor including forming anactive pattern on a substrates the active pattern having two or moresurfaces on which channel regions are to be formed, forming a gateinsulating layer on the channel regions, and forming a patterned gateelectrode on the gate insulating layer while maintaining a shapeconformal to the active pattern.

In one embodiment, forming the patterned gate electrode comprises:forming a conductive layer for a gate electrode on the gate insulatinglayer conformally to the active pattern; forming a sacrificial layer forplanarizing an upper surface of the substrate by filling a step of theconformally formed conductive layer for the gate electrode; and formingthe gate electrode by patterning the conductive layer and thesacrificial layer.

In one embodiment, forming the sacrificial layer comprises: forming thesacrificial layer on the entire surface of the resulting structurehaving the conductive layer; and filling the step of the conformallyformed conductive layer by planarizing the sacrificial layer.

In one embodiment, the sacrificial layer is an amorphous silicon layer.

Planarizing the sacrificial layer can include using a chemicalmechanical polishing (CMP) process. In one embodiment, a polishing stoplayer is formed on the conductive layer after the conductive layer isformed. The polishing stop layer can be formed of a material selectedfrom the group consisting of SiO₂, SiN, SiON, and a combination thereof.

In one embodiment, before the patterning of the conductive layer and thesacrificial layer, an insulating layer is formed on the substrate, ahard mask is formed by patterning the insulating layer using a patternfor defining the gate electrode, and the gate electrode is formed byetching the conductive layer and the sacrificial layer using the hardmask as an etch mask.

In one embodiment, after the forming the gate electrode, the remainingsacrificial layer is removed. In one embodiment, the remainingsacrificial layer is removed by a selective wet etching process. In oneembodiment, a tetramethylammonium hydroxide (TMAH) solution, or a mixedsolution of nitric acid, HF and water, is used during the selective wetetching process.

In one embodiment, before the removing of the sacrificial layer, a firstspacer is formed on the gate electrode and the lateral surfaces of thesacrificial layer remaining on the gate electrode, wherein in theremoving of the sacrificial layer, the first spacer formed on thelateral surface of the sacrificial layer is removed together with thesacrificial layer so that the first spacer remains on the lateralsurfaces of the gate electrode. The first spacer can be formed at atemperature of 550 degrees C. or less. The first spacer can be formed ofa material selected from the group consisting of SiO₂, SiN, SiON, and acombination thereof.

In one embodiment, after removing the sacrificial layer, shallowlow-concentration ion implantation is performed by implanting ions intothe active pattern using the gate electrode and the first spacer asion-implantation masks; a second spacer is formed on the lateralsurfaces of the first spacer; and deep high-concentration ionimplantation is performed by implanting ions into the active patternusing the first and second spacers and the gate electrode asion-implantation masks.

In one embodiment, forming the active pattern comprises: preparing asilicon-on-insulator (SOI) wafer; and forming the active pattern bypatterning a silicon layer of the SOI wafer.

In one embodiment, forming the active pattern includes forming aplurality of active patterns on the substrate, the active patternshaving two or more surfaces on which the channel regions are to beformed.

According to another aspect of the present invention, there is provideda multi-gate transistor including an active pattern formed on asubstrate, the active pattern having two or more surfaces on whichchannel regions are to be formed, a gate insulating layer formed on theactive pattern, a patterned gate electrode formed on the gate insulatinglayer and having a shape conformal to the active pattern, and asource/drain region formed in the active pattern located in both lateralsurfaces of the gate electrode.

In one embodiment, the height of the gate electrode is in a range of500-1,000 Å.

In one embodiment, a first spacer is formed on the lateral surfaces ofthe gate electrode conformally to the active pattern. The first spacercan be formed of a material selected from the group consisting of SiO₂,SiN, SiON, and a combination thereof. The first spacer can have athickness in a range of 100-200 Å. In one embodiment, a second spacer isformed on the lateral surface of the first spacer conformally to theactive pattern. In one embodiment, the source/drain region comprises alightly doped drain region aligned with the gate electrode and the firstspacer and a heavily doped region aligned with the second spacer.

In one embodiment, the active pattern is a patterned silicon layer of anSOI wafer.

In one embodiment, the active pattern includes a plurality of activepatterns having two or more surfaces on which channel regions are to beformed.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description ofpreferred aspects of the invention, as illustrated in the accompanyingdrawings in which like reference characters refer to the same partsthroughout the different views. The drawings are not necessarily toscale, emphasis instead being placed upon illustrating the principles ofthe invention. In the drawings, the thickness of layers and regions areexaggerated for clarity. In addition, when a layer is described to beformed on another layer or on a substrate, the layer may be formed onthe other layer or on the substrate, or a third layer may be interposedbetween the layer and the other layer or the substrate.

FIG. 1A is a perspective view showing a structure of a multi-gatetransistor according to one embodiment of the present invention.

FIG. 1B is a cross-sectional view taken along a line X-X′ shown in FIG.1A.

FIG. 1C is a cross-sectional view taken along a line Y-Y′ shown in FIG.1A.

FIG. 2 is a perspective view showing a structure of a multi-gatetransistor according to another embodiment of the present invention.

FIGS. 3A through 3J are cross-sectional views successively illustratingsteps of a method of fabricating a multi-gate transistor according tothe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In embodiments of the present invention, a fabrication method of amulti-gate transistor capable of controlling a gate electrode profilewith stable profile reproducibility and a multi-gate transistorfabricated thereby are provided.

According to embodiments of the present invention, an active pattern isformed on a substrate, the active pattern having two or more surfaces onwhich channel regions are to be formed and a gate insulating layer isformed on the channel regions. A conductive layer for a gate electrodeis formed on the gate insulating layer and a sacrificial layer is formedthereon. The sacrificial layer is planarized for performing aphotolithography process on the sacrificial layer and the conductivelayer for the gate electrode. Preferably, chemical mechanical polishing(CMP) is used to planarize the sacrificial layer and a polishing stoplayer functioning as a stop layer against CMP is formed between theconductive layer for the gate electrode and the sacrificial layer. Thus,when the surface planarizing process is performed for forming the gateelectrode, the sacrificial layer is removed in a subsequent process. Asa result, the conductive layer having a desired thickness can be formedand a profile of the gate electrode can be reproduced in a stablemanner.

Multi-gate transistors to which a method of fabricating an activestructure according to the present invention can be applied include adouble-gate transistor having channel regions on two surfaces of anactive pattern and a tri-gate transistor having channel regions on threesurfaces of an active pattern.

These multi-gate transistors of the invention also include transistorsused in highly integrated semiconductor memory devices such as a dynamicrandom access memory (DRAM) device, a static RAM (SRAM) device, a flashmemory device, a ferroelectric RAM (FRAM) device, a magnetic RAM (MRAM)device, and a parameter RAM (PRAM) device, micro electro mechanicalsystem (MEMS) devices, optoelectronic devices, display devices, andprocessors such as a central processing unit (CPU) and a digital signalprocessor (DSP). In particular, embodiments of the present invention canbe effectively used to fabricate an active structure of a transistor fora logic device or an SRAM device requiring a great driving current toensure fast operation.

Hereinafter, preferred embodiments of the present invention will bedesribed in detail with reference to FIGS. 1A through 3J.

FIG. 1A is a perspective view showing a structure of a multi-gatetransistor 100 according to one embodiment of the present invention,FIG. 1B is a cross-sectional view taken along a line X-X′ in FIG. 1A,and FIG. 1C is a cross-sectional view taken along a line Y-Y′ in FIG.1A.

As shown, the multi-gate transistor 100 according to the presentinvention includes an active pattern 230 a formed on a substrate 215,the active pattern 230 a having two or more surfaces on which channelregions are to be formed, a gate insulating layer 240 a formed on theactive pattern 230 a, a gate electrode 250 a formed conformally on thegate insulating layer 240 a according to a shape of the active pattern230 a, and a source/drain region 235 formed on the active patternslocated in both lateral surfaces of the gate electrode 250 a.

In the following specification, description will be given of theinvention with reference to the multi-gate transistor 100 having atri-gate transistor having channel regions formed on three surfaces ofthe active pattern 230 a. It will be understood that the invention isapplicable to other multi-gate transistor structures.

The substrate 215 may include a bulk semiconductor substrate 210 and aninsulating layer 220 stacked on the semiconductor substrate 210. Theactive pattern 230 a may be a silicon-on-insulator (SOI). Thus, theactive pattern 230 a is preferably an SOI layer stacked on theinsulating layer 220 formed on the bulk semiconductor substrate 210 inorder to enhance a drain induced barrier lowering (DIBL) effect in atri-gate transistor. The SOI substrate may be formed using a bondingprocess or a Separation by IMplantation of OXygen (SIMOX) process. Thebulk semiconductor substrate 210 may be formed of only silicon orsilicon and germanium. In addition, a GaAs substrate may also be used asthe bulk semiconductor substrate 210 and the invention is not limitedthereto. Nitride, oxide or sapphire may be used as the insulating layer220. Although the substrate 215 using a silicon-on-insulator (SOI)substrate has been described by way of example, the present invention isnot limited thereto and the substrate 215 can also be embodied as ageneral semiconductor substrate.

The active pattern 230 a may be formed of a semiconductor material. Forexample, the active pattern 230 a may be formed of silicon (Si),germanium (Ge), silicon germanium (Si_(x)Ge_(y)), gallium arsenic(GaAs), InSb, GaP and carbon nanotube, and the present invention is notlimited thereto. In order to improve an electrical characteristic of themulti-gate transistor 100, it is preferable that an ideal singlecrystalline film be used as the active pattern 230 a. In this case, themulti-gate transistor 100 can be used in a high-speed operation devicesuch as a microprocessor. Here, if a device is not required to meetstrict specification requirements, like a liquid crystal display (LCD),a polycrystalline film can be used as the active pattern 230 a.

As shown in FIGS. 1A and 1B, the active pattern 230 a according to thepresent invention has a lower surface 234 formed at a portion contactingthe substrate 215, a pair of lateral surfaces 231 and 233 formed atopposite sides of the lower surface 234, and an upper surface 232opposite to and facing the lower surface 234. Channel regions are formedon at least two among three surfaces including the lower surface 234 andthe lateral surfaces 231 and 233 of the active pattern 230 a.

In the multi-gate transistor 100 according to the present invention, asshown in FIG. 1B, the gate insulating layer 240 a is formed on threesurfaces of the active pattern 230 a. That is, the gate insulating layer240 a is formed on the upper surface 232 and lateral surfaces 231 and233 of the active pattern 230 a, on which the channel regions are to beformed.

The gate insulating layer 240 a may be formed using an oxide layer, athermally grown silicon dioxide layer, silk, polyimide, or a highdielectric material. Here, the oxide layer may be formed using dry etchusing O₂ gas at a temperature of 1000-1100° C., wet etch in anatmosphere of water vapor at a temperature of 1000-1100° C., HCloxidation using a mixture gas of O₂ gas and HCl gas, oxidation using amixture gas of O₂ gas and C₂H₃Cl₃ gas, oxidation using a mixture gas ofO₂ gas and C₂H₂Cl₂ gas, or the like. The high dielectric material may beformed by forming an Al₂O₃ layer, a Ta₂O₅ layer, a HfO₂ layer, a ZrO₂layer, a hafnium silicate layer, a zirconium silicate layer, or acombination thereof using atomic layer deposition.

Preferably, the gate insulating layer 240 a is formed to a thickness of5-50 Å. As the thickness of the gate insulating layer 240 a is reduced,a material having a higher dielectric constant (k) is required, forexample, HfO₂, Ta₂O₅, Al₂O₃, PZT, or the like.

As shown in FIGS. 1A through 1C, the gate electrode 250 a is formed onthe gate insulating layer 240 a. It is preferable that the gateelectrode 250 a is formed on the gate insulating layer 240 a formed onthree surfaces of the active pattern 230 a. The gate electrodeconducting layer 250 a may be formed by using only a doped polysiliconlayer or a metal layer, by sequentially stacking a doped polysiliconlayer and a metal layer, or by sequentially stacking a doped polysiliconlayer and a metal silicide layer. The metal layer is formed of atungsten layer, a cobalt layer, or a nickel layer. Suitable examples ofthe metal silicide layer include a tungsten silicide layer, a cobaltsilicide layer, and a nickel silicide layer. The doped polysilicon layerthat is widely used at present is formed by LPCVD using SiH₂Cl₂ and PH₃gas. The gate electrode 250 a is conformally formed along a step of theactive pattern 230 a.

As shown in FIG. 1B, three channels and three gates g1, g2 and g3 areformed by the gate insulating layer 240 a surrounding the upper surface232 and the lateral surfaces 231 and 233 of the active pattern 230 a andthe gate electrode 250 a formed on the gate insulating layer 240 a.Three channels are formed on the upper surface 232 and the lateralsurfaces 231 and 233 of the active pattern 230 a. The gate width of themulti-gate transistor 100 is equal to the sum of the widths of threechannels. That is, the gate width of the multi-gate transistor 100 isequal to the sum of the heights of both lateral surfaces 231 and 233 andthe width of the upper surface 232 of the active pattern 230 a.

FIG. 2 is a perspective view showing a structure of a multi-gatetransistor according to another embodiment of the present invention. Asshown in FIG. 2, the gate width of a multi-gate transistor 150 can beincreased by forming a single gate electrode 170 on a plurality ofactive patterns 160 a, 160 b and 160 c. In FIG. 2, reference numeral 160denotes a source/drain region to which the plurality of active patterns160 a, 160 b and 160 c are connected. As shown in FIG. 2, the gateelectrode 170 of the multi-gate transistor 150 is conformally formedalong steps of the plurality of underlying active patterns 160 a, 160 band 160 c. Further, a first spacer 180 and a second spacer 190 formed ina side of the gate electrode 170 are conformally formed along the stepsof the plurality of underlying active patterns 160 a, 160 b and 160 c.

Here, the gate electrode 170 shown in FIG. 2 performs the same functionas the above-described gate electrode 250 a of FIGS. 1A through 1C andcan be fabricated by the same fabrication method as the gate electrode250 a. In addition, the first spacer 180 and the second spacer 190 shownin FIG. 2 may perform the same functions as a first spacer 285 andsecond spacer 290 of FIGS. 1A through 1C and can be fabricated by thesame fabrication method as the first spacer 285 and the second spacer290, respectively, which will be described below.

As shown in FIG. 1B, in the multi-gate transistor 100 according to thepresent invention, the upper surface 232 and the lateral surfaces 231and 233 of the active pattern 230 a can be formed to a thickness of 500Å or less. Preferably, the upper surface 232 of the active pattern 230 ais formed to a width of about 400 Å and the lateral surfaces 231 and 233of the active pattern 230 a are formed to a length of about 350 Å.

It is preferable that a height Hg of the gate electrode 250 a shown inFIG. 1B is larger than the lengths of the lateral surfaces 231 and 233of the active pattern 230 a. Preferably, the height Hg of the gateelectrode 250 a is in a range of 500-1,000 Å. More preferably, theheight Hg of the gate electrode 250 a is in a range of 750-850 Å.

As shown in FIG. 1C, the gate length of the multi-gate transistor 100according to the present invention corresponds to a distance Lg betweenlateral surfaces 251 and 252 of the gate electrode 250 a. It ispreferable that the gate length Lg is formed to a thickness of 600 Å orless. Referring to FIGS. 1A through 1C, it is preferable that thelateral surfaces 251 and 252 of the gate electrode 250 a and the lateralsurfaces 231 and 233 of the active pattern 230 a are formed in aperpendicular direction.

Referring back to FIG. 1A, in the multi-gate transistor 100 according tothe present invention, the source/drain region 235 is formed on theactive pattern 230 a located at either side of the gate electrode 250 a.The source/drain region 235 can be doped with either n-type or p-typedopant impurities. The source/drain region 235 according to the presentinvention may include a lightly doped drain (LDD) region based onshallow ion implantation and a heavily doped region based on deep ionimplantation.

The LDD region is formed by implanting ions in the vicinity of theactive pattern 230 a in a low concentration using the gate electrode 250a as an ion-implantation mask. According to another embodiment of thepresent invention, as shown in FIG. 1C, in order to ensure the effectivechannel length during formation of the LDD region, the LDD region isaligned with the first spacer 285 by performing ion implantation usingthe gate electrode 250 a and the first spacer 285 formed on the lateralsurface of the gate electrode 250 a as ion-implantation masks.Generally, in a case of an n-type transistor, low energy implantation isperformed on arsenic (As) or phosphorus (P) having a concentration ofabout 10¹³ atoms/cm². Further, in a case of a p-type transistor, lowenergy implantation is performed on boron (B) having a concentration ofabout 10¹³ atoms/cm². The thus formed LDD region lowers an electricfield, thereby preventing a hot carrier effect.

Here, the first spacer 285 used as a mask for low-concentration shallowion implantation may be not only a single layer, such as an SiO₂ layer,but also a multi-layered thin film in which an SiN layer and an SiO₂layer are stacked. Further, the first spacer 285 can be formed to athickness in a range of 100-200 Å.

As described above, the first spacer 285 is formed on the lateralsurface of the gate electrode 250 a, thereby ensuring the effectivechannel length in a subsequent process for forming the LDD region andpreventing the gate electrode 250 a from being etched away in asubsequent wet etching process.

As shown in FIG. 1A, deep ion implantation is performed on the activepattern 230 a using the first spacer 285, the second spacer 290 and thegate electrode 250 a formed on the lateral surface of the gate electrode250 a as ion-implantation masks, thereby forming the heavily dopedregion in an aligned manner with respect to the second spacer 290.Generally, in a case of an n-type metal-oxide semiconductor (MOS)transistor, high-concentration ion implantation is performed on arsenic(As) or phosphorus (P) having a concentration of about 10¹⁴-10¹⁵atoms/cm² at an implant energy of several tens of kiloelectron volts(keV). Further, in a case of a p-type MOS transistor, high-concentrationion implantation is performed on boron (B) having a concentration ofabout 10¹⁴-10¹⁵ atoms/cm² at an implant energy of several tens ofkiloelectron volts (keV).

Here, the second spacer 290 used as the mask for deep ion-implantationis made of an insulating material and is formed on the lateral surfaceof the gate electrode 250 a. The second spacer 290 according to thepresent invention may be formed of SiN, SiO₂, SiON, or a combinationthereof. The second spacer 290 preferably has a thickness in a range of20-2,000 Å.

Hereinafter, the method of fabricating the multi-gate transistor 100according to the present invention will be described with reference toFIGS. 3A through 3J.

As shown in FIG. 3A, the substrate 215 on which an active layer 230 isformed is prepared. Here, the substrate 215 may include a bulksemiconductor substrate 210 and an insulating layer 220 formed on thesemiconductor substrate 210, and SOI can be used as the active pattern230 a.

As shown in FIG. 3B, the active layer 230 is patterned to form theactive pattern 230 a. Here, the active pattern 230 a is formed throughthe following processes. First, an insulating layer for a hard mask isdeposited on the active layer 230 and the insulating layer for the hardmask is etched and patterned using photoresist. The active layer 230 isetched using the insulating layer for the hard mask as an etch mask,thereby forming the active pattern 230 a. Thereafter, the remaininginsulating layer for the hard mask can be removed by wet etching.Alternatively, the active pattern 230 a may be formed by performing dryetching the active layer 230 after the photoresist is directly coated onthe active layer 230 without using the insulating layer for the hardmask to perform a photolithography process. Thereafter, the remainingphotoresist can be removed by ashing and stripping processes.

In addition, ion implantation for adjusting a threshold voltage may beperformed on the entire surface of the resulting structure having theactive pattern 230 a.

Then, as shown in FIG. 3B, the gate insulating layer 240 a is formed onthe upper surface 232 and both lateral surfaces 231 and 233 (see FIG.1B) of the active pattern 230 a. The gate insulating layer 240 aaccording to the present invention can be formed to a thickness of 5-50Å by wet oxidation, dry oxidation, CVD, or the like.

As shown in FIG. 3C, a conductive layer 250 for a gate electrode isformed on the entire surface of the resulting structure having the gateinsulating layer 240 a. The conductive layer 250 according to thepresent invention can be formed using a chemical vapor deposition (CVD),such as low-pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), orplasma enhanced CVD (PECVD). Thus, the conductive layer 250 isconformally formed according to the shape or step of the underlyingactive pattern 230 a.

A polishing stop layer 260 is formed on the conductive layer 250. Ifneeded, ion implantation for doping can be performed on the conductivelayer 250. A thermal process can be performed for the purpose ofactivating doped ions.

Here, a material such as SiO₂, SiN, SiON, or a combination thereof canbe used as the polishing stop layer 260. The polishing stop layer 260can be formed to a thickness of about 50-2,000 Å using such a method asCVD or atomic layer deposition (ALD). The polishing stop layer 260 canfunction not only as a stop layer for a subsequent CMP process(hereinafter, referred to as a CMP stopper), but also as a buffer layerfor preventing the conductive layer 250 from being damaged during theion-implantation process. Thus, it is preferable that the polishing stoplayer 260 be formed to a thickness of 300 Å or more to be used as theCMP stopper. Under a working environment in which a buffer layer forion-implantation for doping the conductive layer 250 with doped ions isnot required, ion implantation for doping is first performed on theconductive layer 250, followed by activating the doped ions, and thepolishing stop layer 260 is then formed on the conductive layer 250.

As shown in FIG. 3D, a sacrificial layer 270 is formed on the polishingstop layer 260. Here, amorphous silicon or polycrystalline silicon canbe used as the sacrificial layer 270, the amorphous silicon orpolycrystalline silicon exhibiting high wet etch selectivity withrespect to the active pattern 230 a made of single crystalline siliconin a subsequent process. Preferably, amorphous silicon exhibiting highwet etch selectivity with respect to the gate electrode 250 a made ofpolycrystalline silicon in a subsequent process is used as thesacrificial layer 270. The sacrificial layer 270 can be formed to athickness of about 200-5,000 Å by CVD or ALD.

Referring to FIG. 3E, a planarized sacrificial layer 270 a is formed bypolishing the sacrificial layer 270 by CMP. Here, the polishing stoplayer 260 can be used as the CMP stopper. Thus, to attain the planarizedsacrificial layer 270 a, CMP is preferably performed until the polishingstop layer 260 is exposed outside. During the CMP, slurry whose etchselectivity ratio of the sacrificial layer 270 a to the polishing stoplayer 260 is 10:1 or higher is preferably used.

An insulating layer 280 is formed on the planarized sacrificial layer270 a thus and the polishing stop layer 260. Here, as the insulatinglayer 280, SiO₂, SiN, SiON or a material consisting of a combinationthereof having a high etch selectivity with respect to the gateinsulating layer 240 a and the conductive layer 250 for the gateelectrode in a subsequent etching process can be used. The insulatinglayer 280 can be formed to a thickness of about 200-2,000 Å by CVD orALD.

Referring to FIG. 3F, the insulating layer 280 is patterned by anetching process using photoresist so that a patterned insulating layer280 a is formed. The remaining photoresist pattern can be removed byashing and stripping processes. Here, the patterned insulating layer 280a is used as a hard mask for forming the gate electrode (250 a shown inFIG. 3G), which will later be described. As shown in FIG. 3F, it ispreferable that the patterned insulating layer 280 a and the activepattern 230 a be formed in a perpendicular direction with respect toeach other.

As shown in FIG. 3G, the polishing stop layer 260, the sacrificial layer270 a and the conductive layer 250 for a gate electrode 250 a are etchedusing the patterned insulating layer 280 a as a hard mask, therebyforming the gate electrode 250 a. Here, a highly selective etchingprocess is preferably employed for the purpose of allowing the patternedinsulating layer 280 a to be less etched than a polishing stop layer 260a and a sacrificial layer 270 b during the etching process. Thepolishing stop layer 260 a and the sacrificial layer 270 b are resultantlayers after the polishing stop layer 260 and the sacrificial layer 270a undergo the etching process. The remaining patterned insulating layer280 a used as the hard mask may be removed by wet etching.

As described above, in order to form the gate electrode 250 a bypatterning the conductive layer 250 for the gate electrode, aphotolithography process for pattern formation is necessarily performed.In addition, in order to perform the photolithography process, thesurface of the gate electrode 250 a must be planarized. In the processfor fabricating the gate electrode 250 a according to the presentinvention, the surface of the gate electrode 250 a is not directlyplanarized but is planarized using the sacrificial 270 a formed on thegate electrode 250 a, followed by performing the photolithographyprocess. Since the gate electrode 250 a conformally formed along thesteps of the active pattern 230 a is not etched in a perpendiculardirection, an initial shape of the gate electrode as deposited for thefirst time by a manufacturer can be maintained. That is to say, since aprofile of the gate electrode 250 a can be controlled by themanufacturer, the profile of the gate electrode 250 a, which greatlyaffects electrical characteristics of a transistor is reproducible in astable manner.

As shown in FIG. 3H, the first spacer 285 can be formed on the lateralsurface of the gate electrode 250 a. The first spacer 285 prevents thegate electrode 250 a from being etched in a subsequent wet etchingprocess performed for removal of the sacrificial layer 270 b. The firstspacer 285 can be formed on the lateral surfaces of the gate electrode250 a and the sacrificial layer 270 b by performing etch back aftercoating an insulating layer on the entire surface of the resultingstructure shown in FIG. 3G by CVD, for example. The first spacer 285formed on regions other than the lateral surface of the gate electrode250 a can be removed in subsequent steps of removing and cleaning thesacrificial layer 270 b.

According to the illustrative embodiment of the present invention, sincethe first spacer 285 is formed on the lateral surface of the gateelectrode 250 a, the first spacer 285 prevents the gate electrode 250 afrom being etched and ensures an effective channel length in asubsequent process for forming the LDD region.

As described above, the first spacer 285 is formed at a predeterminedtemperature or less to prevent the sacrificial layer 270 b fromundergoing a phase change so that the sacrificial layer 270 b is changedfrom an amorphous silicon phase into a polycrystalline silicon phase. Ifthe sacrificial layer 270 b formed of amorphous silicon is crystallizedinto polycrystalline silicon in a process for forming the first spacer285, the gate electrode 250 a may be etched in the subsequent wetetching process performed for removal of the sacrificial layer 270 b.Generally, amorphous silicon is crystallized at a temperature of about600 degrees C. or more to become polycrystalline silicon. Thus, it ispreferable that the formation process of the first spacer 285 beperformed at a low temperature of 550 degrees C. or less.

According to the present invention, both a single layer such as an SiO₂layer and a multi-layered thin film such as a stack of an SiN layer andan SiO₂ layer can be used as the first spacer 285. Further, a materialsuch as SiO₂, SiN, SiON, or a combination thereof can also be used asthe first spacer 285. The first spacer 285 can be formed to a thicknessin a range of 100-200 Å.

As shown in FIG. 3I, the sacrificial layer 270 b is removed by wetetching. At this time, the wet etching preferably has high selectivityso that the sacrificial layer 270 b is etched while the gate electrode250 a is not etched. Further, with respect to the active pattern 230 a,only the sacrificial layer 270 b is preferably selectively etched. Thus,in the illustrative embodiment of the present invention, when thesacrificial layer 270 b is removed by wet etching, an etchant havinghigh etching selectivity of the sacrificial layer 270 a to the activepattern 230 a formed of single crystalline silicon, that is, greaterthan 10:1, can be used. Examples of such etchant include atetramethylammonium hydroxide (TMAH) solution, and a mixed solutioncontaining nitric acid, HF and water mixed in a ratio of 100:40:x(x=1-3).

As shown in FIG. 3I, the LDD regions are formed by performing shallowlow-concentration ion implantation in the vicinity of the surface of theactive pattern 230 a located at either side of the gate electrode 250 afrom which the sacrificial layer 270 b has been removed using the gateelectrode 250 a and the first spacer 285 formed on the lateral surfaceof the gate electrode 250 a as ion-implantation masks. At this time,generally known deep halo implantation can be performed on the activepattern 230 a located directly under the gate electrode 250 a. Inaddition, after removing the first spacer 285 formed on the surface ofthe gate electrode 250 a, the lightly doped drain region can be formedaccording to the process condition.

An insulating layer for a spacer is coated on the entire surface of theresulting structure shown in FIG. 31 by CVD or the like, followed byperforming an etch-back process. As a result, as shown in FIG. 3J, thesecond spacer 290 is formed on the lateral surface of the first spacer285. The polishing stop layer 260 a shown in FIG. 31 can be removed bydry etching the insulating layer for forming the second spacer 290 andthen cleaning the same.

Referring to FIG. 3J, the heavily doped region is formed by performingdeep ion implantation on the active pattern 230 a using the secondspacer 290 formed on the lateral surface of the gate electrode 250 a andthe gate electrode 250 a as ion-implantation masks.

The source/drain region of the multi-gate transistor 100 according tothe present invention is defined by the LDD region and the heavily dopedregion formed within the active pattern 230 a.

Thereafter, an interlayer dielectric (not shown) is formed and a contactplug (not shown) contacting the source/drain region, another contactplug (not shown) contacting the gate electrode 250 a, and an upperinterconnect (not shown), are formed by general methods, therebycompleting the multi-gate transistor according to the present invention.

As described above, according to the present invention, a profile of agate electrode can be reproduced in a stable manner, thereby providing amulti-gate transistor having improved performance and a fabricationmethod thereof.

Preferred embodiments of the present invention have been disclosedherein and, although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1. A method of fabricating a multi-gate transistor comprising: formingan active pattern on a substrate, the active pattern having two or moresurfaces on which channel regions are to be formed; forming a gateinsulating layer on the channel regions; and forming a patterned gateelectrode on the gate insulating layer while maintaining a shapeconformal to the active pattern.
 2. The method of claim 1, whereinforming the patterned gate electrode comprises: forming a conductivelayer for a gate electrode on the gate insulating layer conformally tothe active pattern; forming a sacrificial layer for planarizing an uppersurface of the substrate by filling a step of the conformally formedconductive layer for the gate electrode; and forming the gate electrodeby patterning the conductive layer and the sacrificial layer.
 3. Themethod of claim 2, wherein forming the sacrificial layer comprises:forming the sacrificial layer on the surface of the resulting structurehaving the conductive layer; and filling the step of the conformallyformed conductive layer by planarizing the sacrificial layer.
 4. Themethod of claim 3, wherein the sacrificial layer is an amorphous siliconlayer.
 5. The method of claim 3, wherein planarizing the sacrificiallayer includes using a chemical mechanical polishing (CMP) process. 6.The method of claim 5, after forming of the conductive layer, furthercomprising forming a polishing stop layer on the conductive layer. 7.The method of claim 6, wherein the polishing stop layer is formed of amaterial selected from the group consisting of SiO₂, SiN, SiON, and acombination thereof.
 8. The method of claim 2, before the patterning ofthe conductive layer and the sacrificial layer, further comprising:forming an insulating layer on the substrate; forming a hard mask bypatterning the insulating layer using a pattern for defining the gateelectrode; and forming the gate electrode by etching the conductivelayer and the sacrificial layer using the hard mask as an etch mask. 9.The method of claim 2, further comprising removing the remainingsacrificial layer after forming the gate electrode.
 10. The method ofclaim 9, wherein the remaining sacrificial layer is removed by aselective wet etching process.
 11. The method of claim 10, wherein oneof a tetramethylammonium hydroxide (TMAH) solution and a mixed solutionof nitric acid, HF and water is used during the selective wet etchingprocess.
 12. The method of claim 9, further comprising, before theremoving of the sacrificial layer, forming a first spacer on the gateelectrode and the lateral surfaces of the sacrificial layer remaining onthe gate electrode, wherein in the removing of the sacrificial layer,the first spacer formed on the lateral surface of the sacrificial layeris removed together with the sacrificial layer so that the first spacerremains on the lateral surfaces of the gate electrode.
 13. The method ofclaim 12, wherein the first spacer is formed at a temperature of 550degrees C. or less.
 14. The method of claim 13, wherein the first spaceris formed of a material selected from the group consisting of SiO₂, SiN,SiON, and a combination thereof.
 15. The method of claim 12, afterremoving the sacrificial layer, further comprising: performing shallowlow-concentration ion implantation by implanting ions into the activepattern using the gate electrode and the first spacer asion-implantation masks; forming a second spacer on the lateral surfacesof the first spacer; and performing deep high-concentration ionimplantation by implanting ions into the active pattern using the firstand second spacers and the gate electrode as ion-implantation masks. 16.The method of claim 1, wherein forming the active pattern comprises:preparing a silicon-on-insulator (SOI) wafer; and forming the activepattern by patterning a silicon layer of the SOI wafer.
 17. The methodof claim 1, wherein forming the active pattern includes forming aplurality of active patterns on the substrate, the active patternshaving two or more surfaces on which the channel regions are to beformed.
 18. A multi-gate transistor comprising: an active pattern formedon a substrate, the active pattern having two or more surfaces on whichchannel regions are to be formed; a gate insulating layer formed on theactive pattern; a patterned gate electrode formed on the gate insulatinglayer having a shape conformal to the active pattern; and a source/drainregion formed in the active pattern located in both lateral surfaces ofthe gate electrode.
 19. The multi-gate transistor of claim 18, wherein aheight of the gate electrode is in a range of 500-1,000 Å.
 20. Themulti-gate transistor of claim 18, further comprising a first spacerformed on the lateral surfaces of the gate electrode conformally to theactive pattern.
 21. The multi-gate transistor of claim 20, wherein thefirst spacer is formed of a material selected from the group consistingof SiO₂, SiN, SiON, and a combination thereof.
 22. The multi-gatetransistor of claim 20, wherein the first spacer has a thickness in arange of 100-200 Å.
 23. The multi-gate transistor of claim 20, furthercomprising a second spacer formed on the lateral surface of the firstspacer conformally to the active pattern.
 24. The multi-gate transistorof claim 23, wherein the source/drain region comprises a lightly dopeddrain region aligned with the gate electrode and the first spacer; and aheavily doped region aligned with the second spacer.
 25. The multi-gatetransistor of claim 18, wherein the active pattern is a patternedsilicon layer of an SOI wafer.
 26. The multi-gate transistor of claim18, wherein the active pattern includes a plurality of active patternshaving two or more surfaces on which channel regions are to be formed.